Staff Digital Design Engineer - CPU Architecture & RISC-V (S)

Overview

Ne.therlands We’re looking for a Staff Digital Design Engineer to take technical ownership of RISC-V-based CPU architecture and subsystem integration in our next-generation neuromorphic SoCs.

In this high-impact role, you’ll lead the design and implementation of advanced CPU cores and digital IPs, from high-level specification to final sign-off.

You’ll be instrumental in driving architectural decisions, RTL development, and SoC integration, while collaborating closely with verification, backend, and software teams.

Design and architect advanced CPU cores and micro-architectures, with particular expertise in RISC-V instruction sets and extensions;Translate high-level architectural requirements in.to detailed micro-architectural specifications for CPU designs;Collaborate with verification engineers to ensure comprehensive testing and validation of CPU IP, including instruction set compliance and performance;Define and implement SoC-level architectures, specifically focusing on the integration of CPU cores and their interaction with o.ther IP and subsystems;Assist in verifying SoC functionality through top-level testing, ensuring robust system performance, especially regarding CPU operation;Perform RTL coding and debugging of CPU cores and related logic using Verilog or System Verilog;Conduct RTL and gate-level simulations to ensure design accuracy and performance for CPU and associated logic;Execute all front-end design tasks for CPU cores, including syn.thesis, STA, formal equivalence checking;Support software-hardware co-design efforts, demonstrating a deep understanding of the SW-HW system and its interaction with the CPU;Drive the development of innovative CPU IP concepts based on high-level product specifications, exploring new architectural paradigms;Evaluate, cus.tomize, and integrate third-party CPU IP or components (e.g., memory management units, interrupt controllers) to enhance system performance;Work closely with analog design, verification to ensure seamless integration and cohesive project development for CPU-centric designs.7+ years of experience in digital design, with a strong focus on CPU architecture and micro-architecture development;Demonstrable experience in designing and implementing RISC-V based CPU cores (e.g., cus.tom cores, modifications to open-source cores);Deep understanding of CPU pipeline stages, memory hierarchies (caches, MMU), interrupt handling, and bus interfaces related to CPU design;Expertise in RTL coding (Verilog/System Verilog) and debugging for complex digital modules, particularly CPU designs;Strong knowledge of SoC architecture and subsystem integration, specifically concerning CPU integration;Proven experience in front-end design tasks for CPU cores, including syn.thesis, STA, and formal equivalence checking;Solid understanding of digital verification methodologies and working collaboratively with verification teams, with a focus on CPU verification;Familiarity with common communication pro.tocols (